The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Applications involving signal processing such as modern communication systems require high accuracy (e.g. 12-14 bit) and high speed (e.g. above 100 Megahertz) digital-to-analog converters (DACs). Complementary DACs convert digital signals (e.g. binary code) into analog signals (e.g. electrical voltage or current).
Referring now to FIG. 1, an exemplary “current-steering” DAC 10 is shown to include a segmentation module 12, a row/column (R/C) address generating module 14, a binary-thermometer (B/T) row decoder 16, a B/T column decoder 18, a R/C selection module 20, latches and switches matrix module 22, and a current matrix module 24. The DAC 10 converts a binary input word including n bits (e.g. 14 bits) into a corresponding analog signal. The segmentation module 12 receives the binary input word and divides the binary input into b least significant bits (LSBs) and n-b, or m most significant bits (MSBs).
The row/column address generating module 14 generates row and column codes, or addresses, based on the MSBs. The B/T row decoder 16 and the B/T column decoder 18 thermometer decode the row and column codes, respectively. The R/C selection module 20 generates control signals based on the thermometer row codes and column codes received from the B/T row decoder 16 and the B/T column decoder 18, respectively. The control signals activate switches within the latches and switches matrix module 22. Each switch respectively controls a unary current source. Additionally, each switch is grouped to a latch (not shown) within the latches and switches matrix module 22. By coupling a latch to a corresponding switch, timing errors within the DAC 10 are minimized. Typically, the current sources are organized in a current matrix module 24 independent of the latches and switches matrix module 22.
FIG. 2 illustrates exemplary unary current sources I0, I1, I2, I3, and Im, referred to collectively as the current sources, of the DAC 10 where m=(2n−1) Each of the current sources generates a substantially constant current. Switches D0, D1, D2, D3, . . . , and Dm correspond to current sources I0, I1, I2, I3, . . . , and Im, respectively. The switches D0, D1, D2, D3, . . . , and Dm respectively receive control signals S0, S1, S2, S3, . . . , and Sm, referred to collectively as the control signals, that selectively drive the switches.